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General • Re: RP2040: Substantial PIO jitter in I2S clock

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I mean on oscilloscope ... GPIO_DRIVE_STRENGTH is clearly seen, but with GPIO_SLEW_RATE cannot tell the difference, loaded or not, even at 400 MHz output drive, maybe a hint, maybe too subtle.
I see the same thing, very difficult to see any difference with the scope for the GPIO_SLEW_RATE option.
Surely, some internal IC nodes must be switching with higher slew rate, externally, with normal loads (even with only the scope), it seems there is almost no difference.
Maybe some RPI expert can tell us more details. :?:
Do you use a resistive DAC ?
I'd like to try.
The resistor DAC is a classic R2R network, with values chosen to meet the requirements of a video output:
  • 4 bits.
  • Maximum output: 0.7V with a 75 ohm load.
  • Output impedance: close to 75ohm.
  • Limit current to acceptable levels for GPIO.
VGA DAC 4bit R2R - bit tests_.png
The 320 ohm resistors are only used in the simulation, actually they are 300 ohm.
This is done to compensate for the output impedance of GPIO pins.
The 75 ohm resistor is not part of the network, it simulates the input of the target video device.
The resistor divider formed by 4.7 and 147 resistors can be modified to fine-tune the output voltage or impedance.
With the values shown (the real ones I used in the PCB), output impedance is 77.7 ohm, and output is a little bit over 0.7V.
Maximum current for GPIO is between 7 and 9mA (depending on the bit).

Theoretically, with 4.7 and 137 ohm, you get 74.8 ohm impedance and 0.701V output.

Of course, for RGB, I have 3 DACs like this in the same PCB.

Statistics: Posted by visenri — Sat Nov 30, 2024 4:06 pm



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